Multilayer printed circuit board structures comprising a layer stack made from a number of layers that are electrically insulating and/or provided with conductor track structures and at least one passive or active electrical component in the interior of the layer stack have recently gained more and more in significance for integrating passive electrical components such as capacitors and resistors, and/or active electrical components such as semiconductor chips, in the interior of a printed circuit board of the so-called multilayer type. The multilayer structure comprises a layer stack made from a number of electrically insulating or dielectric layers lying one above another, for example made from a prepreg resin material, with interposed electrical conductor structure planes that include suitable substrates with applied conductor track structures. The layer stack is completed, for example, by lamination or pressing with the use of dielectric prepreg layers, at least some of the layers laid one above another being provided on one or both sides with an electrically conducting layer that is structured into a desired electrical conductor pattern before the layers are laid one above another to form the layer stack. To this end, use is frequently made of an epoxy resin as substrate material with a copper cladding for so-called inner plies, that is to say layers located in the interior of the layer stack and provided with conductor track structures. In order to structure the so-called outer plies, that is to say the external layers provided with conductor track structures, a copper foil is mostly laid onto a dielectric prepreg layer and is firmly connected to the prepreg layer by the pressing operation.
In order to integrate an active and/or passive electrical component into a printed circuit board in such a way, it is known to fix such a component in a region free of conductor tracks on an electrically insulating base layer provided with conductor tracks, before one or more further layers are then applied to complete the layer stack, and the overall structure is laminated together and pressed. It is customary in this case for there to adjoin the base layer carrying the component a next dielectric layer that is of full-area design or is provided in the region of the electrical component with a window or cutout region. In the present context, a window is understood as an opening completely penetrating the relevant layer, whereas a cutout is understood as a recess formed on one side only in the relevant layer at a depth smaller than the layer thickness. Terminal contact pads of the electrical component are contact-connected to conductor structures on the base layer, or to conductor structures in other planes of the layer stack with the aid of vias, which are also to be understood for the sake of simplicity in the present context as blind hole contacts that end on the contact pads. Alternatively, the electrical component is fixed on the base layer in an electrical contacting region thereof and electrically connected directly to conductor structures there. Multilayer printed circuit board structures of these various types are described, for example, in laid-open patent application DE 196 27 543 A1, patent EP 1 230 680 B1 and the journal article W. Bauer and S. Purger, Integration aktiver und passiver Bauelemente in die Leiterplatte—Alles inklusive—[Integration of active and passive components in the printed circuit board—including all—], EPP November 2003, page 48.
German laid-open patent application DE 31 25 518 A1 describes a thin wiring arrangement for connecting electrical components to an external circuit that comprises a substrate for holding the electrical component, a first insulating layer, arranged on the substrate and made from an organic material, a wiring that is constructed on the first insulating layer and is connected to the electrical component, a second insulating layer, arranged on the first insulating layer and made from an organic material, and terminals, arranged on the first insulating layer, which lie exposed in the second insulating layer and are connected to the wiring. The substrate used is a metallic or ceramic substrate having a cutout in which the electrical component is held. The wiring constructed on the first insulating layer makes contact with terminals provided on the top side of the electrical component. In an embodiment described with reference to U.S. Pat. No. 3,763,404, the wiring for the component is formed on a top side of a flexible wiring substrate that is provided with a window region for making contact with the electrical component arranged underneath the level of the wiring substrate, that is to say terminal structures of the wiring are guided through the window region to the top-side terminal pads of the component. This contacting of the component is simultaneously used for mechanical preassembly of the component on the wiring, that is to say wiring substrate, wiring and component are, for example, prefabricated by means of a continuous tape band process.
Patent DE 690 31 350 T2 discloses an electronic multilayer package having a multilayer ceramic substrate that consists of a multiplicity of insulating and signal/reference voltage layers lying one above another, and which includes on its top side one or more cutouts for holding one or more semiconductor chips arranged next to one another. The chip(s) located in the respective cutout is/are seated there on a binder layer that is formed on the bottom of the cutout and, for example, is formed from a eutectic gold alloy or an epoxy or polyimide material. In the case of a number of chips that are to be placed in a cutout, these form part of a chip structure that is introduced into the cutout and additionally includes above the chips intermediate and innerchip wiring planes that consist of multiple line/metal interconnections and insulating plies interposed therebetween. A multilayer thin film structure made from a multiplicity of insulating layers and metallization layers is applied to the substrate top side provided with the chip(s) introduced, the metallization layers being electrically connected by vias to top-side terminal pads of the respective chip or to the intermediate and innerchip wiring planes of the chip structure.
U.S. Pat. No. 5,401,688 discloses a multilayer printed circuit board structure comprising a layer stack made from a number of layers provided with conductor track structures and in which at least one semiconductor chip is embedded between two of these layers. In the lamination process of the multiply multilayer printed circuit board structure, electrical contact is made between bump terminal pads of the chip and conductor structures of the neighboring layer that are aligned therewith.